FIFORDEN=Val_0x0, RSTSEL=Val_0x0, BYTEEN=Val_0x0, FIFOSEL=Val_0x0, FDBGEN=Val_0x0, PKTIE=Val_0x0, FIFOWREN=Val_0x0, STSIE=Val_0x0, RSTALL=Val_0x0, DBGMOD=Val_0x0
FIFO Debug Access Control and Status Register
| FDBGEN | FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled. When this bit is reset, it indicates that the FIFO can be accessed only through a master interface. 0 (Val_0x0): FIFO debug access is disabled 1 (Val_0x1): FIFO debug access is enabled |
| DBGMOD | Debug Mode Access to FIFO When this bit is set, it indicates that the current access to the FIFO is read, write, and debug access. In this mode, the following access types are allowed: Read and Write access to Tx FIFO, TSO FIFO, and Rx FIFO Read access is allowed to Tx Status FIFO. Write access to the Tx FIFO Read access to the Rx FIFO and Tx Status FIFO 0 (Val_0x0): Debug mode access to FIFO is disabled 1 (Val_0x1): Debug mode access to FIFO is enabled |
| BYTEEN | Byte Enables This field indicates the number of data bytes valid in the data register during Write operation. This is valid only when PKTSTATE is 0x2 (EOP) and Tx FIFO or Rx FIFO is selected. 0 (Val_0x0): Byte 0 valid 1 (Val_0x1): Byte 0 and Byte 1 are valid 2 (Val_0x2): Byte 0, Byte 1, and Byte 2 are valid 3 (Val_0x3): All four bytes are valid |
| PKTSTATE | Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO. Tx FIFO: 0x0: Packet data 0x1: Control word 0x2: SOP data 0x3: EOP data Rx FIFO: 0x0: Packet data 0x1: Normal status 0x2: Last status 0x3: EOP |
| RSTALL | Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0. Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets. 0 (Val_0x0): Reset all pointers is disabled 1 (Val_0x1): Reset all pointers is enabled |
| RSTSEL | Reset Pointers of Selected FIFO When this bit is set, the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0. Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets. 0 (Val_0x0): Reset pointers of selected FIFO is disabled 1 (Val_0x1): Reset pointers of selected FIFO is enabled |
| FIFORDEN | FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0. Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets. 0 (Val_0x0): FIFO read is disabled 1 (Val_0x1): FIFO read is enabled |
| FIFOWREN | FIFO Write Enable When this bit is set, it enables the Write operation on selected FIFO when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled, that is FDBGEN bit is 0. Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets. 0 (Val_0x0): FIFO write is disabled 1 (Val_0x1): FIFO write is enabled |
| FIFOSEL | FIFO Selected for Access This field indicates the FIFO selected for debug access: 0 (Val_0x0): Tx FIFO 1 (Val_0x1): Tx Status FIFO (only read access when SLVMOD is set) 2 (Val_0x2): TSO FIFO (cannot be accessed when SLVMOD is set) 3 (Val_0x3): Rx FIFO |
| PKTIE | Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is generated when EOP of received packet is written to the Rx FIFO. 0 (Val_0x0): Receive packet available interrupt status is disabled 1 (Val_0x1): Receive packet available interrupt status is enabled |
| STSIE | Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is generated when Transmit status is available in slave mode. 0 (Val_0x0): Transmit packet available interrupt status is disabled 1 (Val_0x1): Transmit packet available interrupt status is enabled |